FIG. 1 shows a configuration example of a conventional memory block 300. This memory block 300 has a memory cell array 310, a storage data input/output port 320, a row address decoder 330, and a control circuit 340.
The memory cell array 310 has, as shown in FIG. 2, a plurality of bit lines BL for transferring data that extends in a row direction, a plurality of word lines WL that extends in a column direction to intersect with a plurality of the bit lines BL perpendicularly, and memory cells ML that are arranged in a matrix and connected to these bit lines BL and word lines WL.
The memory cell ML is of a DRAM structure and has an access transistor T and a capacitor C. The capacitor C has its one end grounded and the other end connected via the access transistor T to the bit line BL. The access transistor T, on the other hand, has its gate connected to a word line WL. Write or read operation to or from this memory cell ML is implemented by activating the word line WL and turning ON the access transistor T as conventionally well known.
The storage data input/output port 320 has a column address decoder 321, an address buffer 322, and an I/O buffer 323. The column address decoder 321 includes an I/O gate (column switch), a sense-amplifier. The column address decoder 321 is supplied with column addresses via the address buffer 322.
In response to the column addresses supplied via the address buffer 322, the column address decoder 321 secures its connection with a plurality of bit lines BL that is connected to a predetermined plurality of column directional memory cells ML in the memory cell array 310, to enable write or read operation of storage data to or from this predetermined column directional memory cells ML through the I/O buffer 323 and the column address decoder 321.
The row address decoder 330, on the other hand, is supplied with row addresses via an address buffer 331. In response to the row addresses supplied via the address buffer 331, the row address decoder 330 activates a word line WL that is connected to predetermined row directional memory cells ML in the memory cell array 310, to enable write or read operation of storage data to or from this predetermined row directional memory cells ML through the I/O buffer 323 and the column address decoder 321.
Further, the control circuit 340 controls operations of these circuits in the memory block 300 based on a control input.
To perform an operation, for example, addition by use of data stored in the above-described memory block 300, augend data and addend data are read sequentially from the memory block 300 and added up by an adder arranged separately from this memory block 300. Therefore, this method of reading the items of data and performing the operations sequentially leads to a disadvantage that a computing speed cannot be increased. Further, since the computing unit is necessary separately from the memory block 300, costs are increased by that much disadvantageously. This holds true also with any other operations such as subtraction.
Further, in image processing, detection of a motion vector is one of the important factors and typically represented by block matching. According to it, with respect to a certain pixel block (reference block) that constitutes part of a certain frame (reference frame), correlation of the reference block and same-shape pixel blocks (candidate blocks) at various positions in a frame (search frame) at a different time point is evaluated and a relative positional shift of the reference block to the candidate block having the highest correlation is regarded as a motion vector in that reference block.
It is to be noted that the search range is an assumed range of the candidate blocks. In evaluation of the correlation, a total sum of absolute difference values of pixel data, for each in-block pixel, between pixels in the reference block and the corresponding pixels in the candidate block, that is, a sum of absolute difference value is used often. Although a sum of absolute difference value of the candidate block in the search range for each reference block is given, the least sum of absolute difference value thereof is regarded as a motion vector that is given in pixel units.
FIG. 3 shows a configuration example of a conventional motion vector detection circuit 200.
This motion vector detection circuit 200 has an input terminal 201 to which an image signal Di of a reference frame is input, a reference frame memory 202 for accumulating this image signal Di of the reference frame, and a search frame memory 203 for accumulating an image signal of a search frame. When the image signal Di of a certain frame is supplied from the input terminal 201 to the frame memory 202 and written in it, an image signal of the immediately preceding frame stored in this frame memory 202 is read and supplied to the frame memory 203 and written in it.
The motion vector detection circuit 200 further has an arithmetic circuit 204 for receiving pixel data of a reference block from the frame memory 202 and pixel data of a plurality of candidate blocks in a search range that corresponds to this reference block from the frame memory 203 to compute and output, for each of the plurality of candidate blocks, an absolute difference value between each of the items of pixel data in these candidate blocks and the pixel data in the reference block.
This arithmetic circuit 204 obtains difference data by adding up, at an addition portion 204b, pixel data of the reference block and two's complement format pixel data of the candidate block converted by a convert-to-two's-complement portion 204a from straight binary format data and by converting this difference data into its absolute value at a convert-to-absolute portion 204c, thereby giving an absolute difference value.
The motion vector detection circuit 200 further has a total-sum-computing portion 205 for obtaining a sum of absolute difference values by accumulating the absolute difference values output from the arithmetic circuit 204 for each of the items of pixel data corresponding to each of the plurality of candidate blocks and an absolute-difference-value-sum-holding portion 206 for holding the sum of the absolute difference values obtained by this total-sum-computing portion 205 for each of the plurality of candidate blocks.
The motion vector detection circuit 200 further has a minimum sum decision portion 207 for detecting a motion vector based on the sum of the absolute difference values held in the absolute-difference-value-sum-holding portion 206 for each of the plurality of candidate blocks, a motion-vector-holding portion 208 for holding the motion vector detected by this minimum sum detection portion 207, and an output terminal 209 for sequentially outputting a motion vector MV of each of the reference blocks held in this motion-vector-holding portion 208. The minimum sum decision portion 207 detects a position of one of the candidate blocks that generates a minimum sum of absolute difference values, as a motion vector.
The following will describe operations of the motion vector detection circuit 200 shown in FIG. 3.
The image signal Di input to the input terminal 201 is supplied to the reference frame memory 202 and accumulated as a reference frame image signal. At the same time, further, an image signal of the immediately preceding frame stored in the frame memory 202 is read and supplied to the frame memory 203 and accumulated as a search frame image signal.
The arithmetic circuit 204 is supplied with image data of a reference block read from the frame memory 202. This arithmetic circuit 204 is further supplied with read pixel data of a plurality of candidate blocks in a search range that corresponds to this reference block. Then, on respective candidate blocks, this arithmetic circuit 204 computes an absolute difference value between the items of pixel data of the plurality of candidate blocks and the items of pixel data of the reference block, for each of the items of the corresponding pixel data, and outputs it.
In such a manner, the absolute difference value output from the arithmetic circuit 204 for each of the items of pixel data corresponding to each of the plurality of candidate blocks is sequentially supplied to the total-sum-computing portion 205, thus obtaining a sum of the absolute values. The sum of the absolute difference values from this total-sum-computing portion 205 for each of the plurality of candidate blocks is supplied to the absolute-difference-value-sum-holding portion 206 and held in it. Based on the sum of the absolute difference values held in the absolute-difference-value-sum-holding portion 206 for each of the plurality of candidate blocks, the minimum sum decision portion 207 detects a position of such one of these candidate blocks as to generate a minimum sum of the absolute difference values as a motion vector, which is held in the motion-vector-holding portion 208.
From the frame memory 202, the arithmetic circuit 204 is supplied with pixel data of the plurality of reference blocks in a reference frame sequentially. Corresponding to the pixel data in each of the reference blocks, pixel data of the plurality of candidate blocks is supplied from the frame memory 203 to the arithmetic circuit 204. Therefore, corresponding to each of the reference blocks, the above operations are repeated by the arithmetic circuit 204, the total-sum-computing portion 205, the absolute-difference-value-sum-holding portion 206, the minimum sum decision portion 207, and the motion-vector-holding portion 208, so that motion vectors in accordance with the reference blocks are detected by the minimum sum detection circuit 207 sequentially and held in the motion-vector-holding portion 208 sequentially.
The motion vectors in accordance with the reference blocks held in the motion-vector-holding portion 208 are read sequentially. These read motion vectors MV are provided to the output terminal 209. The read motion vectors MV are used in motion compensation processing to perform, for example, motion compensation predictive encoding.
A flowchart of FIG. 4 shows a procedure for detecting a motion vector MV in the above-described motion vector detection circuit 200.
First, at step ST21, the process starts and, at step ST22, reads an image signal stored in the reference frame memory 202 and writes this image signal as an image signal of a search frame into the search frame memory 203. At step ST23, the process inputs the image signal Di of a reference frame from the input terminal 201 and writes this image signal to the reference frame memory 202.
Next, at step ST24, the process reads pixel data of a reference block from the reference frame memory 202 and, at step ST25, reads from the search frame memory 203 pixel data of such a candidate block in a search range as to correspond to that reference block and converts this straight binary format data into two's complement format data at the convert-to-two's-complement portion 204a at step ST26.
At step ST27, the process adds up the straight binary format pixel data of the reference block and pixel data of the candidate block converted into the two's complement format data, to obtain difference data. At step ST28, the process converts that difference data into its absolute value, thus generating an absolute difference value between the pixel data of the reference block and that of the candidate block.
Next, at step ST29, the process computes a sum of the absolute difference values between a certain reference block and predetermined candidate blocks at the total-sum-computing portion 205 and stores it in the holding portion 206 at step ST30. At step ST31, the process decides whether generation of the sum of absolute difference values between the certain reference block and every candidate block has ended. If such is not the case, the process returns to step ST25, to shift to processing of generating a sum of absolute difference values between the certain reference block and the next candidate block. Otherwise, the process goes to step ST32.
At step ST32, the process detects a position of a candidate block that generates a minimum sum of the absolute difference values among them, based on the sums of absolute difference values held in the holding portion 206 corresponding to the certain reference block, as a motion vector. At step ST33, the process stores this detected motion vector in the z motion-vector-holding portion 208.
Next, at step ST34, the process decides whether this processing of detecting the motion vector for all of the reference blocks in the reference frame has ended. If such is not the case, the process returns to step ST24, to shift to processing of detecting a motion vector that corresponds to the next reference block. Otherwise, at step ST35, the process sequentially outputs motion vectors MV that respectively correspond to the reference blocks held in the motion-vector-holding portion 208 and, at step ST36, ends the processing.
The above motion vector detection circuit 200 has had a disadvantage of higher costs due to a necessity of the circuits for computing difference data, an absolute value, a total sum, etc. as arithmetic circuits.